A dynamic random access memory (DRAM) cell includes a transistor coupled to a capacitor. One type of DRAM cell employs the use of a trench capacitor coupled to a vertical transistor. FIG. 1 shows a cross-sectional view of a conventional trench capacitor 140. As shown, the trench capacitor is disposed in a lower portion 111a of a trench 110 formed in a substrate 105. A pad layer 190 is provided on the surface of the substrate. The pad layer comprises silicon nitride layer 192 over a silicon oxide layer 191. The pad layer facilitates processing of the trench capacitor.
The trench capacitor includes bottom and top sections 141a-b. A buried plate 144 surrounds the trench in the bottom section of the capacitor. A highly conducting semiconductor material or metal 142 (fill material) fills the trench, separated from the buried plate by a node dielectric layer 146. The buried plate, for example, is commonly coupled to other capacitors of the array and to a reference voltage, such as VDD/2. A thick dielectric collar 165 lines the trench sidewalls in the top section of the capacitor.
A vertical transistor (not shown) is provided in the upper portion 111b of the trench. To isolate the capacitor from the transistor, an isolating dielectric layer 148 is provided on top of the capacitor. To couple the trench capacitor to the transistor, a buried diffusion region 132 is provided. The diffusion region is created by outdiffusing dopants from the fill material through a buried strap 174 located between the collar and isolation dielectric layer.
FIG. 2 shows a conventional process for forming a buried strap. After the capacitor is formed, the trench fill material is recessed below the surface of the substrate, exposing the collar in the upper portion 111b of the trench. The exposed portion of the collar is then removed by, for example, a wet etch. The etch overetches the collar, recessing it below the surface of the trench fill material 142. The over etch creates a divot 271. An amorphous silicon layer 273 is then deposited to line the trench and fill the divot. The amorphous silicon layer is etched by, for example, an isotropic reactive ion etch (RIE) or wet etch to remove the amorphous silicon layer 273 from the pad layer and storage node material, thus leaving the amorphous silicon layer in the divot to form the buried strap.
However, due to the small dimensions of the divot and to the non-ideal conformal deposition of the amorphous silicon layer, a void 277 may be created during the divot fill process. The void results in incomplete filling of the divots, which can degrade the coupling between the transistor and capacitor. This can adversely affect the performance and/or reliability of the memory cell.
From the foregoing discussion, it is desirable to provide a trench capacitor which avoids the problems associated conventional buried straps.